1. Field of the Invention
This invention relates to a memory writing apparatus and more particularly to a PROM writer or gang writer for writing data in a plurality of memories such as PROMs.
2. Description of the Related Art
A PROM writer is a system for writing data in a memory, e.g., an EPROM, OTP, EEPROM, or RAM. A gang writer is known as a type of PROM writer which simultaneously writes data in a plurality of memories.
For instance, it is possible for one gang writer to simultaneously write data in eight, sixteen or thirty two 256 kbit EPROMs. Generally, several tens to several hundreds of such gang writers are provided in a memory department of a memory maker in which desired items of data are written in memories before the memories are shipped.
FIG. 1 shows a basic construction of conventional gang writers. A gang writer A shown in FIG. 1 has an operational section 1 to which an interface circuit 2 is connected. A write control circuit 3 is connected to the interface circuit 2, an a buffer memory (or a master memory) 4 to which a decision circuit 5 is connected is connected to the write control circuit 3. A memory holding section 7 is connected to the interface circuit 2. A power supply circuit 6 for supplying necessary power to the components of the gang writer A, namely, the circuits 1 to 5 and a plurality of memories 71 disposed in the memory holding section 7 is also provided in the gang writer A.
A gang writer B disposed adjacent to the gang writer A has the same construction as that of the gang writer A. A host computer (not shown) is connected to the interface circuits 2 of these gang writers.
The operation of these gang writers will be described below with reference to the flow chart of FIG. 2.
After the power supply circuits 6 of the gang writers A and B have been turned on (step 8), the plurality of memory modules 71 in which desired data will be written are placed in the memory holding section 7 (step 9), and items of data to be written are prepared (step 10). That is, the buffer memories 4 are loaded with items of data to be written which are supplied from the host computer via the interface circuits 2.
Thereafter, a blank check of each of the memories 71 placed the memory clearing sections 7 is performed by the write control circuit 3 in order to check whether or not the memory 71 contains no data (step 11). The blank check is performed for every memory 71 placed in the memory holding section 7 incrementally (step 12a).
The data in the buffer memory 4 is written in each memory 71 by the write control circuit 3, and comparison between the data written in the memory 71 and the data stored in the buffer memory 4 is made by the decision circuit 5 (step 14). The comparison (12b) is then repeated so that the step 14 is conducted with respect to all the memories 71. Thereafter, the data is read out from each memory 71 by the write control circuit 3 and a comparison between the data thereby read out and the data in the buffer memory 4 is performed (step 15). The step 15 is also conducted with respect to all the memories 71 incrementally (step 12c).
If an abnormality is detected in step 11, 14, or 15, the process proceeds to the step 13 to start error processing.
After the process of writing the data in the memories 71 has been completed, the memories 71 are removed from each memory holding section 7 (step 16), and the power supply circuits 6 are turned off (step 17).
In the conventional system, however, only eight to thirty two memories can be written with data by one gang writer. It is therefore necessary for a semiconductor maker to prepare a large number of gang writers in order to mass-produce and ship written memories, and a large investment and a large installation area are therefore needed. There is also a problem in distributing data to respective gang writers.